Refer to the model given below, which circuit is designed? LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY design IS PORT(a, b, c : in BIT; x, y : out BIT); END design; ARCHITECTURE arch1 OF design IS COMPONENT xor2 IS PORT (i1, i2 : IN STD_LOGIC; o : OUT STD_LOGIC); END COMPONENT; COMPONENT and2 IS PORT(a1, a2 : IN STD_LOGIC; P : OUT STD_LOGIC); END COMPONENT; COMPONENT or2 IS PORT(d1, d2 : IN STD_LOGIC; r : OUT STD_LOGIC); END COMPONENT; SIGNAL s1, s2, s3, s4, s5 : STD_LOGIC; BEGIN X1: xor2 PORT MAP(a, b, s1); X2 : xor2 PORT MAP(s1, c, x); X3: and2 PORT MAP(a, b, s2); X4 : and2 PORT MAP(a, c, s3); X5: and2 PORT MAP(b, c, s4); X6: or2 PORT MAP(s2, s3, s5); X7: or2 PORT MAP(s4, s5, y); END arch1;

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Question:
Refer to the model given below, which circuit is designed?

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY design IS
PORT(a, b, c : in BIT;
x, y : out BIT);
END design;
ARCHITECTURE arch1 OF design IS
COMPONENT xor2 IS
PORT (i1, i2 : IN STD_LOGIC;
o : OUT STD_LOGIC);
END COMPONENT;
COMPONENT and2 IS
PORT(a1, a2 : IN STD_LOGIC;
P : OUT STD_LOGIC);
END COMPONENT;
COMPONENT or2 IS
PORT(d1, d2 : IN STD_LOGIC;
r : OUT STD_LOGIC);
END COMPONENT;
SIGNAL s1, s2, s3, s4, s5 : STD_LOGIC;
BEGIN
X1: xor2 PORT MAP(a, b, s1);
X2 : xor2 PORT MAP(s1, c, x);
X3: and2 PORT MAP(a, b, s2);
X4 : and2 PORT MAP(a, c, s3);
X5: and2 PORT MAP(b, c, s4);
X6: or2 PORT MAP(s2, s3, s5);
X7: or2 PORT MAP(s4, s5, y);
END arch1;

1.Half adder

2.Comparator 2- bits

3.Full adder

4. Can’t be determined

Posted Date:-2022-02-09 07:26:48

More MCQS Questions and answers

  1. In which part of the VHDL code, components must be declared?
  2. Which of the following is the correct order for a structural model in VHDL?
  3. Which of the following is the right way to leave a port unconnected?
  4. __________ mapping is less error prone.
  5. A component has 3 ports- two inputs(a and b) and one output(y). Which of the following statement is for the positional mapping of the component?
  6. How many ways are there in VHDL to map the components?
  7. How to declare a 2 input OR gate in the structural modeling?
  8. Refer to the model given below, which circuit is designed? LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY design IS PORT(a, b, c : in BIT; x, y : out BIT); END design; ARCHITECTURE arch1 OF design IS COMPONENT xor2 IS PORT (i1, i2 : IN STD_LOGIC; o : OUT STD_LOGIC); END COMPONENT; COMPONENT and2 IS PORT(a1, a2 : IN STD_LOGIC; P : OUT STD_LOGIC); END COMPONENT; COMPONENT or2 IS PORT(d1, d2 : IN STD_LOGIC; r : OUT STD_LOGIC); END COMPONENT; SIGNAL s1, s2, s3, s4, s5 : STD_LOGIC; BEGIN X1: xor2 PORT MAP(a, b, s1); X2 : xor2 PORT MAP(s1, c, x); X3: and2 PORT MAP(a, b, s2); X4 : and2 PORT MAP(a, c, s3); X5: and2 PORT MAP(b, c, s4); X6: or2 PORT MAP(s2, s3, s5); X7: or2 PORT MAP(s4, s5, y); END arch1;
  9. What is the property of Positional mapping?
  10. Which of the following function is used to map the component?
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